COMP4 Instruction Set and Operating Instructions ================================================ by Michael Robinson (Permission to copy with attribution granted for noncommercial use) Description: ------------ COMP4 is a Harvard architecture computer, with an 8 bit program address and a 16 bit data address. The program memory is 32 bits wide and is nonvolatile. The data memory is 8 bits wide and has a general bus architecture for memory-mapped I/O. The lowest 12 bits are used for addressing volatile data memory. There are 3 programmer-accessible registers: an accumulator, a page register, and an indirection register. The upper 8 bits of the data address are stored in the page register, while the lower 8 bits come from either the instruction or from the indirection register. Instruction Set: ---------------- Each instruction is 32 bits wide, broken into three distinct pieces, called I1, I2, and I3. I1: +--+--+--+--+--+--+--+--+ | R| Opcode |Dest | I| +--+--+--+--+--+--+--+--+ | | | \__ Indirection bit: 0 = use I2 for data address | | | 1 = use indirection register | | \_______ Destination of result: 00 = Accumulator | | 01 = Data memory/device | | 10 = Indirection register | | 11 = Page register | \_________________ Opcode (see table below) \________________________ Reserved 0000 = ACC = contents of accumulator, F = 1 if zero 0001 = MEM = contents of device/memory, F = 1 if zero 0010 = XOR = exclusive OR accumulator and memory, F = 1 if zero 0011 = CLR = result is zero, F = 1 0100 = NOA = One's complement of accumulator, F = 1 if zero 0101 = NOM = One's complement of memory, F = 1 if zero 0110 = AND = AND accumulator and memory, F = 1 if zero 0111 = OR = OR accumulator and memory, F = 1 if zero 1000 = RLA = Rotate Left accumulator, F = most significant bit 1001 = RRA = Rotate Right accumulator, F = most significant bit 1010 = RLM = Rotate Left memory, F = most significant bit 1011 = RRM = Rotate Right memory, F = most significant bit 1100 = ADD = Add accumulator and memory, F = carry 1101 = INA = add 1 to accumulator, F = carry 1110 = INM = add 1 to memory, F = carry 1111 = (unused) I2 is contains the lower 8 bits of the data address of the memory operand for the instruction. It is used if the I bit of I1 is zero. If the I bit of I1 is one, then I2 is unused and the indirection register is used instead. I3 contains two 8 bit words, which contain the two possible locations of the next program address. These are selectable by the program address bit 8 from the front panel and by the F bit during execution. That is, the contents of I3 with bit 8 clear is the next program address if the F bit is clear. Operating Instructions: ----------------------- Switches and descriptions: POWER = Applies power to the processor board and front panel. Note that this destroys the contents of the data memory. Power is not removed from the DC power supply by this switch. RESET = Places the sequencer into a state to execute the current instruction from the beginning, clears the accumulator and the page register. If not resuming execution of a stopped program, press RESET before starting a program. ENABLE/HALT = Starts/Stops program execution. MANUAL/AUTO = Switches between single-step execution and free-running execution. Only valid when execution is ENABLED. STEP = Single-steps the clock when in MANUAL execution. Also can pause execution in AUTO. WRITE ENABLE/READ = Applies only to memory/device data interactions. When in READ, the contents at the BUS ADDRESS are displayed in the BUS DATA. When in WRITE ENABLE, the device will accept WRITE commands. WRITE = Transfer data from the switches to the destination specified by the selector switch. Selector switch: PAGE = DATA switches will write to the page register (high 8 bits of BUS ADDRESS) DEV = DATA switches will write to the memory/device at the address specified by the ADDRESS switches when in WRITE ENABLE. When in READ, the contents of the address specified by the ADDRESS switches is displayrd in the BUS DATA lights. STATE = the DATA switches will write to the state register, which holds the current program address. I1 = the DATA switches will write to the I1 word of the instruction addressed by the ADDRESS switches. I2 = the DATA switches will write to the I2 word of the instruction addressed by the ADDRESS switches. I3 = the DATA switches will write to the I3 word of the instruction addressed by the ADDRESS switches. In this mode (only), bit 8 of the ADDRESS switches is active and selects between the two possible branch destinations. DATA switches = Used to enter data ADDRESS switches = Used to specify addresses